I need the help for lab3 for VLSI cadence project design. I need it to be finished in two days. Please view the whole pdf carefully and when you think you are capable to do it on time and complete perfectly, let me know. I don’t responds to random messages

University of Southern California Department of Electrical Engineering – Systems

EE 477 Laboratory #3 (worth 20% of final grade) Final Project: Neuron Design updated 11/18 4:05 PM Changed/added

remarks in red, Testing Table Added Due 12/3/18 5:00 PM

There will be no extensions so plan your time accordingly!

Required contents of the report appear in purple.

This is a long lab so be sure you scroll to the end to see all the information. Be sure to follow the rules given below near the end of this lab document.

The Digital Neurons This lab is the design of two special-purpose digital circuits that mimic neurons (brain cells) Be sure to finish and test your schematic of each neuron before you start the neuron layout.

The Two Neurons:

There are two neurons with 5 inputs to each neuron:

a data input to the neuron, D that could be different every clock cycle a single-bit inhibitory input I, Load control signal, that allows the output firing flip flop to be loaded with a new value, Set control signal that sets the flip flop by loading Vdd., and a clock with duty cycle of your choice.

Name your signals as shown in bold above, with D1 being the first neuron data input, and D2 the second one. The output of the neurons should be named AP1 and AP2. It is important you follow this naming convention so we can verify that your circuit works. You can create inverted signals like NotLoad in the neuron itself.

The basic Neuron Function:

Each data input and control input is a single bit. The inhibitory input I is a single bit. It prevents the neuron from firing as long as it is held to “1” (Vdd) The neuron output contains one firing flip-flop you designed in Lab 2, and the output of the flip flop AP1 or AP2 represents the outputs of the two neurons. The neurons “fire” when their inputs D have the sequence 1001 for Neuron 1 or 1111 for Neuron 2 and I =0. Each neuron loads 1 into the output flip flop for one clock cycle when the input sequence is correct and then resets it by loading 0 into the output flip flop on the next clock cycle. After the positive edge of the clock, if the neuron fires, the output of the firing flip-flop AP goes from low to high. The output remains high until the next rising clock, when it is lowered. Load is normally held high, but is lowered if we want to emulate a neuron failing to fire due to lack of sleep or similar circumstance. Note that you might find a way to use the compound gate you designed in Lab 1. You do not have to use it at all.

For example, if the inputs are 1111 in sequence, the output flip flop of Neuron 2 will be set (fire) and AP will go high, but will ignore the next data input and will reset the flip flop instead.

Design the circuit to be a Mealy Machine, where the output (the firing flip flop) is derived from the present state and the inputs during the current clock cycle. The next state of the flip flop is also a function of the present state and the inputs.

A block diagram of the neuron is shown below.

Sample Timing Diagram for the Two Neurons:

Below is a sample timing diagram for the neurons that you will need to simulate correctly. This just shows how the neurons are supposed to behave. A required test sequence will be provided by the weekend.

The Laboratory Steps: Testing Strategy:

Here is a testing strategy that might be useful to you: Design the neuron schematic block by block and test after you add each block. Then design the neuron layout and test each part as you build it. Repeat this for the second neuron. Design and test at each stage.

Design and Test Steps:

Each NEURON

1. Design your neuron circuit schematic and create a Cadence circuit (schematic) diagram using the circuits/cells you have designed in Labs 1 and 2. You cannot design new cells for Lab assignment 3 unless you had problems with the other labs or lost points. Include your logic/gate level diagram for your neurons.

2. Simulate your neuron schematics to ensure that your two designs work correctly. Set takes priority over other signals. I (inhibit takes priority otherwise). Use the following sequence of inputs for initial testing of your schematic:

a) Set load to 1 and keep it high. All other inputs except clock (and set if you assert it high) should be 0, including I. Set your neuron flip flop.

b) Set load to 1 and keep it high. Then test your neuron by sequencing through the inputs shown in the timing diagram and the test table.

c) Now set load to 0 (zero). Set the data inputs to produce outputs 11, and I = 0. The flip flop output should remain zero.

3. Lay out your neurons.

4. Use LVS to verify your layouts prior to SPECTRE simulation. Important note: Any pins in your layout labeled the same should be physically connected to each other.

5. Simulate your neuron layouts with SPECTRE to ensure that your design works correctly using the same sequence of inputs as in Step 2, and measure the smallest clock period that is possible for both neurons. Show the waveforms you used to measure the clock period.

a. For each neuron show all inputs D, Set, Load and I together in a panel and in a second panel show the output AP and clock together. (note: not following instructions will lead to deduction of points). There should be 4 panels, 2 for each neuron.

b. Submit a zoom-in of the same waveforms around the time the output transitions occur.

Note: Be sure each output AP transition occurs before the next falling edge of the clock. The output transition should reach at least 90% of Vdd when rising or 10% of Vdd when falling, before the falling edge of the clock.

TEST INPUTS/OUTPUTS for the two Neurons Test data for Neural Network – Test a few clock cycles before testing the entire circuit Time T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 INPUTS Load 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Set 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 I1, I2 Inhibit

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D1 0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 D2 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 OUTPUTS AP1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 AP2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 All state FF’s

0 1 X X X X X X X X X X X X X

X – unique to your design

Rules: 1. You can use any combination of multiple clocks you wish, but only clock is an input to the circuit and you will have

to design circuits to generate the other clocks. 2. You need to generate all inverted inputs, including notclock and notload. They are not inputs to the circuit. You

need to generate them if you need them. 3. You must use the cells you designed in labs 1 and 2 to build your design. Do not change the circuit structure of

your cells unless your cells do not meet the requirements of lab 1a, lab 1b, lab 2a or lab 2b (i.e. you lost points). You can rearrange the layout slightly or resize transistors as needed while still meeting the requirements of labs 1 and 2. Do not change the methodology by rotating transistors, rearranging transistors, connecting inside the cell on different layers, or changing your interconnection strategy (for example, you might decide that all inputs come

in the top of the cell, so you can’t change that). You can move ntaps and ptaps around. 4. You must have ntaps and ptaps according to the rules. Make sure your ohmic contacts (ntaps and ptaps) meet the

following requirement: Every cell should have a well and substrate contact, including transmission gates, and of course the taps should be connected to Vdd and Gnd. For larger cells, include at least two contacts per 50×50 lambda, one for the psubstrate and the other for the nwell. Every separate block of nwell should have at least one ohmic contact. For all your contacts, you will get the best performance if you use multiple minimum-size contacts for large contact areas and not large contacts, as Cadence will do for you automatically.

5. You can tune the circuits by changing transistor sizes as needed or to squeeze out empty space while still meeting the requirements of labs 1 and 2. You can modify the layout of your cells from Labs 1 and 2 in minor ways in Lab 3 if you can see some ways to make the circuits smaller or faster. You can rotate and flip cells about the x and y axes.

6. You cannot remove unused inputs or unused logic from your cells. 7. You can use metal layers 1-4 for each neuron, and layers 1-6 for any external connections that go to the

inputs/outputs of the neurons. 8. All signals should use the names we have given. 9. As in Lab 2, the output transition of the flip flops including any setup time at any following flip flop inputs should

occur before the next falling edge of the clock. 10. For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already

selected. 11. On your final two-neuron layout, all inputs and outputs to the circuit must be routed to the edges of the layout and

must be labeled using the pin names. Final Report Contents: Include in this lab report, in order:

1. A cover page showing name, student number, email address, date, the final area and delay of your two final neuron designs, and AREA-DELAY product. Your report file type should be lastnamefirstname.pdf. Do not submit other file formats, like .doc or .txt. The delay you should measure with SPECTRE simulations of your layout for your final neural network result is the clock cycle or clock period of the neural network layout assuming correct operation. Your output should appear before the clock falls again. The faster your clock cycle, the faster your circuit will function. Measure the area of your design in square microns. Your area should be the bounding box area of your design. If your design is not rectangular, include the wasted area in your area calculation. Compute the area-delay product of your neural network design and report it clearly at the beginning of the report so we can find it. Compute an area-delay product that is the area in square microns times the clock period. If you compute the area-delay product wrong, or you do not compute it you will lose points.

2. A description of the two neurons you built, including a transistor-level and gate-level circuit diagram (schematic) printed from Cadence, your simulation results (including waveform images) and a description of how your circuit was constructed using existing cells.

3. A floorplan of the neurons. A floorplan shows where on the layout you placed functions, without showing the details of the functions. Cadence might have a tool to do this for you but you need to draw it yourself for clarity. Try this link to see an example. You do not have to draw your floorplan over your layout image but it helps clarity.

4. Your neuron layout images and neuron and neuron layout simulation results as images. Make sure the layout and simulation images are of high enough resolution so that we can zoom in to check things. Put your input and output waveforms onto separate traces so we can read them more easily

5. A description of the simulation experiments you ran with SPECTRE for the neuron and neural network. Include (not in the report but as separate files) 1. SPECTRE netlist files for both schematic and layout of the neurons, generated by Cadence, which will include the technology file, the graphical stimulus files and the circuitry netlist. We need every netlist file you used for every simulation so that we can run your simulations in case your results are unexpected. 2. High resolution images of your neuron layouts and waveform files. This is so we can view the layout properly to check details. Make the waveform signals thick enough for us to see them.

Tar or zip this report along with the files specified above. Other formats besides Tar or zip will not be accepted. Upload your report to D2L, including your layout and simulation files as a TAR file so that we can test (simulate) your circuit to be sure it performs as specified. IMPORTANT: Once you upload there will be no deletions or reuploads allowed. All files should be in a single Tar or Zip file, uploaded to DEN. All layouts must be in color unless you obtain prior permission. Failure to follow these instructions could result in deduction of points.

Discussion:https://www.google.com/search?q=chip+floorplan&client=firefox-b-1&tbm=isch&source=iu&ictx=1&fir=6A5mb—D3RvqM%253A%252ChcZMPewsxuviPM%252C_&usg=__lxmzQvAluY3bz0Kh1IMLsSmKpFw%3D&sa=X&ved=0ahUKEwjujLjHzKHaAhVnwlQKHdvVA_UQ9QEITjAD#imgrc=6A5mb—D3Rv

For this lab, you can use any layout strategy you choose as long as it fits the cell methodology you have already selected. The goal is to minimize the area·delay product. Designs that are more square, rather than long, thin rectangles, tend to be better designs. The designer with the lowest area-delay product will win a prize, a gift certificate from Amazon.com. Pay close attention to the specific delay you are to measure.

End of Lab 3

 
******CLICK ORDER NOW BELOW TO GET THE ANSWER TO THIS ASSIGNMENT OR ANY OTHER ASSIGNMENT, DISCUSSION, ESSAY, HOMEWORK OR QUESTION*******."

Leave a Reply

Your email address will not be published.